Dynamic Random Access Memories (DRAMs) are widely used due to many advantages, such as large capacity, high speed and low cost. Nowadays, DRAMs have been developed to have various types. For example, in high performance applications, the first-generation DDR (Double Data Rate) has been developed to the fifth-generation DDR5. In low power consumption applications, LPDDR (Low Power Double Data Rate) has been developed to LPDDR2.
FIG. 1 illustrates a structural diagram of a common DRAM in existing techniques. Referring to FIG. 1, the DRAM includes a memory array 10, a control logic circuit 20 and an interface conversion logic circuit 30. The memory array 10, which occupies a largest area in the DRAM, includes plenty of memory cells configured to store data. Generally, a memory array can be divided into a plurality of banks with the same size and structure. As shown in FIG. 1, the memory array includes eight banks, each of which has its own data bus and control bus that are independent from those of other banks. In some occasions, there may be a set of banks sharing one data bus and one control bus which are independent from data buses and control buses shared by other sets. The control logic circuit 20 includes a plurality of circuits, such as a memory array control circuit, a row address latch circuit, a column address latch and a bit selection logic circuit. The control logic circuit 20 is configured to control operations of the DRAM, process DRAM protocol, and convert writing and reading request on a DRAM interface into access to each bank. The interface conversion logic circuit 30 is used for data serial-to-parallel conversion. As the DRAM needs to use a relatively narrow data bus interface to reduce Printed Circuit Board (PCB) wiring difficulty and improve reliability of the memory system, the interface conversion logic circuit 30 is configured to convert a data bus which is connected with banks and has relatively great data width into a data bus on the DRAM interface which has relatively small data width. However, the interface conversion logic circuit 30 may cause greater power consumption, and the smaller data bus width may restrain the improvement on DRAM reading rate.
To obtain a wider DRAM data bus, those skilled in the art have developed DRAM packaging methods from Thin Shrink Small Outline Package (TSSOP) to Ball Grid Array (BGA) package and stacked package. In one existing solution, a DRAM data bus having ultra-wide data width is used in a die-to-die package method (namely, bonding and connecting two dies at a time successively), which greatly increases data width of DRAM and reduces power consumption. However, in the above solution, a structure and package of the DRAM needs to be modified greatly, thus, it is not compatible with a DRAM commonly used in these days. That is to say, it is quite difficult to popularize the above solution.
Another existing technique is provided, called wafer-to-wafer package. In wafer-to-wafer package, two wafers with the same size are bonded directly, where sizes of logic regions and distribution patterns of pins on the two wafers should be identical. When the bonding is completed, the logic regions on the two wafers are connected to each other. Single chip pairs are formed after the bonded wafers are sliced, each single chip pair includes two chips connected to each other. In this package method, the chips on the two wafers are connected to each other correspondingly in one step, which is different from the die-to-die package where only two chips are connected to each other in one step and chip pairs are formed successively. Therefore, cost is reduced in the wafer-to-wafer package.
However, a wafer-to-wafer package method leads to a low yield. Since each chip pair has two chips respectively on the two wafers, to ensure the chip pair is non-defective, each of the two chips is required to be non-defective. If either of the two wafers has a low yield, it may lead to a decrease of the yield of chip pairs formed by bonding and connecting the two wafers. For example, a DRAM wafer and a System on Chip (SoC) wafer are used in wafer-level package. Assuming a yield of the SoC wafer is 98% and a yield of the DRAM wafer is 90%, then a yield of chip pairs after package is 0.98*0.9=88.2%. The yield (88.2%) is acceptable, because not many qualified Soc chips are wasted. Considering the cost reduce brought by the wafer-to-wafer package, the yield loss is reasonable in this case. For another example, the yield of the DRAM wafer is 60%, thus, the yield of chip pairs after package is 58.8%, which leads to a great waste of qualified SoC chips.
More related information can be found in Chinese patent publication No. CN102543967A.